View MT46H32M32LFCM-75IT_8139968.PDF datasheet online --- IC-ON-LINE

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? products and specifications disc ussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 1gb: x16, x32 mobile ddr sdram features advance ? pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_1.fm - rev. a 02/07 en 1 ?2007 micron technology, inc. all rights reserved. mobile ddr sdram mt46h64m16lf ? 16 meg x 16 x 4 banks mt46h32m32lf ? 8 meg x 32 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com features ? endur-ic? technology ?v dd/ v dd q = 1.70?1.95v ? bidirectional data strobe per byte of data (dqs) ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? four internal banks for concurrent operation ? data masks (dm) for masking write data?one mask per byte ? programmable burst lengths: 2, 4, or 8 ? concurrent auto precharge option is supported ? auto refresh and self refresh modes ? 1.8v lvcmos-compatible inputs ? on-chip temperature sensor to control self refresh rate ? partial-array self refresh (pasr) ? deep power-down (dpd) ? status read register (srr) ? selectable output drive (ds) ? clock stop capability ? 64ms refresh table 1: configuration addressing architecture 64 meg x 16 32 meg x 32 configuration 16 meg x 16 x 4 banks 8 meg x 32 x 4 banks refresh count 8k 8k row addressing 16k (a0?a13) 8k (a0?a12) column addressing 1k (a0?a9) 1k (a0?a9) notes: 1. only available for x16 configuration. 2. only available for x32 configuration. table 2: key timing parameters speed grade clock rate (mhz) cl = 3 access time -6 166 5.5ns -75 133 6.0ns options marking ?v dd /v dd q ? 1.8v/1.8v h ? configuration ? 64 meg x 16 (16 meg x 16 x 4 banks) ? 32 meg x 32 (8 meg x 32 x 4 banks) 64m16 32m32 ?plastic package ? 60-ball vfbga (10mm x 11.5mm) 1 ? 90-ball vfbga (10mm x 13mm) 2 ck cm ? timing ? cycle time ? 6ns @ cl = 3 ? 7.5ns @ cl = 3 -6 -75 ? operating temperature range ? commercial (0 to +70c) ? industrial (?40c to +85c) none it
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48mtoc.fm - rev. a 02/07 en 2 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram table of contents advance table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 standard mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 temperature-compensated self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 partial-array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 output driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 status register read (srr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 stopping the external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 deep power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 truncated reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 deep power-down (dpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48mlof.fm - rev. a 02/07 en 3 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram list of figures advance list of figures figure 1: 1gb mobile ddr part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: functional block diagram (64 meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: functional block diagram (32 meg x 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 60-ball vfbga assignment ? 10mm x 11.5 mm (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 90-ball vfbga ball assignment ? 10mm x 13mm (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: standard mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 7: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 9: srr timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 10: status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 11: clock stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 12: mobile dram state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 14: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 17: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 18: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 19: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 20: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 21: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 22: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 23: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 24: consecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 25: nonconsecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 26: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 27: write-to-read ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 28: write-to-read ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 29: write-to-read ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 30: write-to-precharge ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 31: write-to-precharge ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 32: write-to-precharge ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 33: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 34: power-down command (in active or precharge modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 35: deep power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 36: deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 37: typical self refresh current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 38: data output timing ? t dqsq, t qh, and data valid window (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 39: data output timing ? t dqsq, t qh, and data valid window (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 40: data output timing ? t ac and t dqsck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 41: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 42: initialize and load mode regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 43: power-down mode (active or prec harge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 44: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 45: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 46: bank read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 47: bank read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 48: bank write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 49: bank write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 50: write ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 51: 60-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 52: 90-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48mlot.fm - rev. a 02/07 en 4 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram list of tables advance list of tables table 1: configuration addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: 60-ball fbga ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: 90-ball vfbga ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: burst definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 6: truth table ? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7: dm operation truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 8: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 9: truth table ? current state bank n - command to bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 10: truth table ? current state bank n ? command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 11: operating temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 12: ac/dc electrical characteristics an d operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 13: capacitance (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 14: i dd specifications and conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 15: i dd specifications and conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 16: i dd 6 specifications and conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 17: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .59 table 18: target normal output drive characteristics (full-drive strength) . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 19: target reduced output drive characteristics (one-half drive strength). . . . . . . . . . . . . . . . . . . . . . .65
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 5 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram fbga part marking decoder advance figure 1: 1gb mobile ddr part numbering fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part numb er. micron?s fbga part marking decoder is available at www.micron.com/decoder . general description the 1gb mobile ddr sdram is a high-speed cmos, dynamic random-access memory containing 1,073,741,824 bits. it is internally configured as a quad-bank dram. each of the x16?s 268,435,456-bit banks is organized as 16,384 rows by 1,024 columns by 16 bits. each of the x32?s 268,435,456-bit banks is organized as 8,192 rows by 1,024 columns by 32 bits. the 1gb mobile ddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer four data words per clock cycle (x32), or two words per clock cycle (x16)at the i/o balls. a single read or write access for the 1gb mobile ddr sdram effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock-cycle data trans- fers at the i/o balls. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a st robe transmitted by the mobile ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte and one for the upper byte and the x32 offering has four data strobes, one per byte. the 1gb mobile ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs, as well as to both edges of ck. speed grade t ck = 6.0ns t ck = 7.5ns -6 -75 it operating temp. standard industrial temp. example part number: mt46h32m32lfxx-75it - mobile configuration mt46 package speed temp. configuration 64 meg x 16 32 meg x 32 64m16lf 32m32lf package 10 x 11.5 vfbga (lead-free) 10 x 13 vfbga (lead-free) h v dd / v dd q v dd /v dd q 1.7v/1.95v ck cm
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 6 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram general description advance read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting co lumn location for the burst access. the mobile ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8. an auto-precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of mobile ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto-refresh mode is provided, along wi th a power saving power down mode. deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. data will not be retained once the device enters deep power- down mode. micron?s 1gb mobile ddr sdram device features endur-ic technology. pairing micron?s advanced memory architecture with innovative endur-ic technology results in mobile ddr devices that exceed current jedec standards, including lower power speci- fications that dramatically redu ce overall power consumption. two self refresh features, temperature-comp ensated self refresh (tcsr) and partial- array self refresh (pasr), offer additional power savings. tcsr is controlled by the auto- matic on-chip temperature sensor. the pasr can be customized using the extended mode register settings. the two features may be combined to achieve even greater power savings. notes: 1. throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. 2. complete functionality is described throughout the document and any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. any specific requirement takes precedence over a general statement.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 7 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram general description advance figure 2: functional block diagram (64 meg x 16) 13 row- addre ss mux c ontrol lo g i c c olumn- addre ss c ounter/ lat c h s tandard mode re g i s ter extended mode re g i s ter 10 c ommand de c ode a0?a13, ba0, ba1 c ke c k# c k cs # we# c a s # ra s # 14 addre ss re g i s ter 1 6 512 (x32) i/o g atin g dm ma s k lo g i c c olumn de c oder bank0 memory array (1 6 ,384 x 512 x 32) bank0 row- addre ss lat c h & de c oder 1 6 ,384 bank c ontrol lo g i c 14 bank1 bank2 bank3 14 9 2 2 refre s h c ounter 1 6 1 6 1 6 2 input re g i s ter s 2 2 2 2 r c vr s 2 32 32 4 32 c k out data dq s ma s k data c k c k in drvr s mux dq s g enerator 1 6 1 6 1 6 1 6 1 6 32 dq0? dq15 ldq s , udq s 2 read lat c h write fifo & driver s 1 c ol0 c ol0 32,7 6 8 s en s e amplifier s ldm, udm c k
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 8 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram general description advance figure 3: functional block diagram (32 meg x 32) 13 ra s # c a s # row- addre ss mux c k cs # we# c k# c ontrol lo g i c c olumn- addre ss c ounter/ lat c h s tandard mode re g i s ter extended mode re g i s ter 10 c ommand de c ode a0?a12, ba0, ba1 c ke 13 addre ss re g i s ter 15 512 (x 6 4) i/o g atin g dm ma s k lo g i c bank0 memory array (8,192 x 512 x 6 4) bank 0 row- addre ss lat c h & de c oder 8,192 bank c ontrol lo g i c 13 bank1 bank2 bank3 13 9 2 2 refre s h c ounter 32 32 32 2 input re g i s ter s 4 4 4 4 r c vr s 4 6 4 6 4 8 6 4 c k out data dq s ma s k data c k c k in drvr s mux dq s g enerator 32 32 32 32 32 6 4 dq0? dq31 dq s 0 dq s 1 dq s 2 dq s 3 4 read lat c h write fifo & driver s 1 c ol0 c ol0 1 6 ,384 s en s e amplifier s dqm0 dqm1 dqm2 dqm3 c k c olumn de c oder
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 9 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram ball assignments and descriptions advance ball assignments and descriptions figure 4: 60-ball vfbga assignment ? 10mm x 11.5mm (top view) notes: 1. d9 is a test pin that must be tied to v ss or v ss q in normal operations. 1 2 3 4 6 7 8 9 5 a b c d e f g h j k v ss q dq14 dq12 dq10 dq8 nc ck# a12 a8 a5 v ss v dd q v ss q v dd q v ss q v ss cke a9 a6 v ss dq15 dq13 dq11 dq9 udqs udm ck a11 a7 a4 v dd q dq1 dq3 dq5 dq7 a13 we# cs# a10 /ap a2 dq0 dq2 dq4 dq6 ldqs ldm cas# ba0 a0 a3 v dd v ss q v dd q v dd q v dd ras# ba1 a1 v dd ball and array test 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 10 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram ball assignments and descriptions advance figure 5: 90-ball vfbga ball assignment ? 10mm x 13mm (top view) notes: 1. d9 is a test pin that must be tied to v ss or v ss q in normal operations. v ss q dq30 dq28 dq2 6 dq24 n c c k# a12 a8 a5 dq8 dq10 dq12 dq14 v ss q v ss v dd q v ss q v dd q v ss q v dd c ke a9 a 6 a4 v ss q v dd q v ss q v dd q v ss dq31 dq29 dq27 dq25 dq s 3 dm3 c k a11 a7 dm1 dq s 1 dq9 dq11 dq13 dq15 v dd q dq17 dq19 dq21 dq23 n c we# cs # a10 /ap a2 dq7 dq5 dq3 dq1 v dd q dq1 6 dq18 dq20 dq22 dq s 2 dm2 c a s # ba0 a0 dm0 dq s 0 dq 6 dq4 dq2 dq0 v dd v ss q v dd q v dd q v ss ra s # ba1 a1 a3 v dd q v ss q v dd q v ss q v dd 1 2 3 4 6 7 8 9 5 a b c d e f g h j k l m n p r ball an d arra y te s t 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 11 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram ball assignments and descriptions advance table 3: 60-ball fbga ball description ball numbers symbol type description g2, g3 ck, ck# input clock: ck is the system clock input. ck and ck# are differential clock inputs. all address and control in put signals are sampled on the crossing of the positive edge of ck and negative ed ge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). g1 cke input clock enable: cke high activates and cke low deactivates the internal clock signals, input buffers, and output drivers. taking cke low allows precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except self refresh exit. all input buffers (except cke) are disabled during power-down and self refresh modes. h7 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. g9, g8, g7 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. f2, f8 udm, ldm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high alon g with that inpu t data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. for the x16, ldm is dm for dq0? dq7 and udm is dm for dq8?dq15. h8, h9 ba0, ba1 input bank address inputs: ba0 and ba1 defi ne to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register is lo aded during a lo ad mode register command. j8, j9, k7, k8, k2, k3, j1, j2, j3, h1, j7, h2, h3, f7 a0?a13 input address inputs: provide the row address for active commands, and the column address and auto-precharge bit (a10) for read or write commands, to select one loca tion out of the memory array in the respective bank. during a precharge command, a10 determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inpu ts also provide the op-code during a load mode register command. a8, b7, b8, c7, c8, d7, d8, e7, e3, d2, d3, c2, c3, b2, b3, a2 dq0?dq15 i/o data input/output: data bus for x16. e8, e2 ldqs, udqs i/o data strobe: output with read data, input with write data. dqs is edge- aligned with read data, centered in wr ite data. it is used to capture data. a7, b1, c9, d1, e9 v dd q supply dq power supply a3, b9, c1, e1 v ss q supply dq ground a9, f9, k9 v dd supply power supply a1, f1, k1 v ss supply ground f3 nc ? no connect: f3 may be left unconnected. d9 test ? d9 is a test pin that must be tied to v ss or v ss q in normal operations.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 12 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram ball assignments and descriptions advance table 4: 90-ball vfbga ball description ball numbers symbol type description g2, g3 ck, ck# input clock: ck is the system clock input. ck and ck# are di fferential clock inputs. all address and co ntrol input signals are sa mpled on the crossing of the positive edge of ck and negative edge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). g1 cke input clock enable: cke high activates and cke low deactivates the internal clock signals, input buffers, and output drivers. taking cke low allows precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except self refresh exit. all input buffers (except cke) are disabled during power-down and self refresh modes. h7 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. g9, g8, g7 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. k8, k2, f8, f2 dm0?dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high alon g with that inpu t data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. for the x32, dm0 is dm for dq0?dq7; dm1 is dm for dq8?dq15; dm2 is dm for dq16?dq23; dm3 is dm for dq24?dq31. h8, h9 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register is loaded during a load mode register command. j8, j9, k7, k9, k1, k3, j1, j2, j3, h1, j7, h2, h3, f7 a0?a12 input address inputs: provide the row address for active commands, and the column address and auto-precharge bit (a10) for read or write commands, to select one location out of the memory array in the respective bank. during a prec harge command, a10 determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op- code during a load mode register command. d9 test ? d9 is a test pin that must be tied to v ss or v ss q in normal operations. f3, f7 nc ? no connect; may be left unconnected. r8, p7, p8, n7, n8, m7, m8, l7 l3, m2, m3, n2, n3, p2, p3, r2, a8, b7, b8, c7, c8, d7, d8, e7, e3, d2, d3, c2, c3, b2, b3, a2 dq0?dq31 i/o data input/output: data bus for x32. l8, l2, e8, e2 dqs0?dqs3 i/o data strobe: output with read data, input with write data. dqs is edge- aligned with read data, centered in wr ite data. it is used to capture data. a7, b1, c9, d1, e9, l9, m1, n9, p1, r7 v dd q supply dq power supply
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 13 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram ball assignments and descriptions advance a3, b9, c1, e1, l1, m9, n1, p9, r3 v ss q supply dq ground a9, f1, r9 v dd supply power supply a1, f9, r1 v ss supply ground table 4: 90-ball vfbga ball description (continued) ball numbers symbol type description
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 14 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram functional description advance functional description the 1gb mobile ddr sdram is a high-speed cmos, dynamic random-access memory containing 1,073,741,824 bits. it is internally configured as a quad-bank dram. each of the x16?s 268,535,456-bit banks is organized as 16,384 rows by 1,024 columns by 16 bits. each of the x32?s 268,535,456bit banks is organi zed as 8,192 rows by 1,024 columns by 32 bits. the 1gb mobile ddr sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o balls. single read or write access for the 1gb mobile ddr sdram consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n - bit wide, one-half-clock-cycle data transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. it should be noted that the dll that is ty pically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal operation, the mobile ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization mobile ddr sdrams must be powered up and initialized in a predefined manner. oper- ational procedures other than those specif ied may result in undefined operation. if there is an interruption to the device powe r, the initialization routine must be followed to ensure proper functionality of the mobile ddr sdram. to properly initialize the mobile ddr sdram, this sequence must be followed: 1. the core power (v dd ) and i/o power (v dd q) must be brought up simultaneously. it is recommended that v dd and v dd q be from the same power source or v dd q must never exceed v dd . assert and hold cke high. 2. once power supply voltages are stable and the cke has been driven high, it is safe to apply the clock. 3. once the clock is stable, a 200s minimum delay is required by the mobile ddr sdram prior to applying an executable co mmand. during this time, nop or dese- lect commands must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect commands for at least t rp time. 6. issue an auto refresh command followed by nop or deselect commands for at least t rfc time. issue a second auto refresh command followed by nop or dese- lect commands for at least t rfc time. two auto refresh commands must be issued. typically, both of these commands ar e issued at this stag e as described above. alternately, the second auto refresh command and nop or deselect sequence can be issued after step 10.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 15 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram register definition advance 7. using the load mode register command, load the standard mode register as desired. 8. issue nop or deselect commands for at least t mrd time. 9. using the load mode register command, load the extended mode register to the desired operating modes. note that the sequ ence in which the standard and extended mode registers are programmed is not critical. 10. issue nop or deselect commands for at least t mrd time. the mobile ddr sdram has been properly initialized and is ready to receive any valid command. register definition mode registers the mode registers are used to define the sp ecific mode of operation of the mobile ddr sdram. there are two mode registers used to specify the operational characteristics of the device. standard mode register the standard mode register bit definition allo ws the selection of burst length, burst type, cas latency, and operating mode, as shown in figure 6 on page 16. reserved states should not be used as it may result in setting the device into an unknown state or cause incompatibility with future versions of mobile ddr sdrams. the standard mode register is programmed via the load mode register command (with ba0 = 0 and ba1 = 0) and will retain the stored informat ion until it is programmed again, the device goes into deep power-down mode, or the device loses power. reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait t mrd before initiating the subse- quent operation. violating any of these requ irements will result in unspecified opera- tion.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 16 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram register definition advance figure 6: standard mode register definition burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length (bl) being programmable (see table 5 on page 18 for details). the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both sequential and inte rleaved burst types. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap when a bo undary is reached. the block is uniquely selected by a1?a i when bl = 2, by a2?a i when bl = 4, and by a3?a i when bl = 8, where a i is the most significant column address bit for a given configuration. the remaining (least significant) address bits are used to specify the starti ng location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programme d to be either sequential or interleaved via the standard mode register. the ordering of accesses within a burst is de termined by the burst length, the burst type, and the starting column address. see table 5 on page 18 for details. m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 standard mode register (mx) address bus 9 7 6 5 4 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0 1 14 m12 0 ? m11 0 ? m10 0 ? m9 0 ? m8 0 ? m7 0 ? m6 m5 m4 m3 m2 m1 m0 valid ? operating mode normal operation all other states reserved 0 0 1 1 mode register definition standard mode register status register read extended mode register reserved m15 0 1 0 1 m16 m13 0 ? 0 1 a13 15
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 17 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram register definition advance cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first outp ut data. the latency can be set to 2 or 3 clocks, as shown in figure 7. for cl = 3, if the read command is registered at clock edge n , then the data will nomi- nally be available at ( n + 2 clocks + t ac). for cl = 2, if the read command is registered at clock edge n , then the data will be nominally be available at ( n + 1 clock + t ac) . figure 7: cas latency c k c k# c k c k# t0 t1 t2 t2n t3 t3n t1n c ommand dq dq s c l = 2 t0 t1 t2 t2n t3 t3n don?t c are tran s itionin g data read nop nop nop c ommand dq dq s c l = 3 read nop nop nop d out n d out n+1 d out n+3 d out n+2 d out n d out n+1 1 n c lo c k a c t 2 n c lo c k a c t
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 18 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram register definition advance operating mode the normal operating mode is selected by issuing a load mode register command with bits a7?a12 (x32) or a7?a13 (x16) each se t to zero, and bits a0?a6 set to the desired values. all other combinations of values for a7?a12/a13 are reserved for future use. reserved states should not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls additional functions beyond those set by the mode registers. these additional functions incl ude drive strength, temperature-compensated self refresh, and partial-array self refresh. the extended mode register is programmed via the load mode register command with ba0 = 0 and ba1 = 1. information in the extended mode register will be retained until it is programmed again, the device goes into deep power-down mode, or the device loses power. temperature-compensated self refresh on this version of the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillat or. programming of the tcsr bits will have no effect on the device. the self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature. partial-array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are shown in figure 8 on page 19. table 5: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2a1a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 19 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram register definition advance write and read commands can still occur du ring standard operation, but only the selected regions of the array will be refreshed during self refresh. data in regions that are not selected will be lost. output driver strength because the mobile ddr sdram is designed for use in smaller systems that are typically point-to-point connections, an option to control the drive strength of the output buffers is provided. drive strength should be sele cted based on the expected loading of the memory bus. there are four allowable settings for the output drivers?25 , 55 , 80 , and 100 internal impedance. these are full, half, quarter, and one-eighth drive strengths, respectively. target output drive characteristics can be found in table 18 on page 64 and table 19 on page 65 for full and half drive settings. figure 8: extended mode register notes: 1. on-die temperature sensor is used in plac e of tcsr. setting these bits will have no effect. a dd ress bus 97 6 54 3 821 pa s r t cs r 1 d s set to ?0? 0 e12 a11 e11 a10 e10 a9 e9 a8 e8 a7 e7 a 6 e 6 a5 e5 a4 e4 a3 e3 a2 e2 a1 e1 a0 e0 10 11 12 e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 partial array s elf refresh c overa g e full array (all b anks) half array (ba1 = 0) quarter array (ba1 = ba0 = 0) reserve d reserve d one-ei g hth array (ba1 = ba0 = row a dd ress m s b = 0) one-sixteenth array (ba1 = ba0 = row a dd ress m s b - 1 = 0) reserve d e 6 0 0 1 1 e5 0 1 0 1 driver s tren g th full stren g th d river half stren g th d river quarter stren g th d rive r one-ei g hth stren g th d river ba0 a12 e14 ba1 e15 1 13 14 15 0 0 1 1 mo d e re g ister definition s tan d ar d mo d e re g ister s tatus re g ister rea d exten d e d mo d e re g ister reserve d e15 0 1 0 1 e14 0 e10 0 ? e11 0 ? e12 0 ? e13 0 ? e9 0 e8 0 ? e7 0 ? vali d ? normal ar operation e13 a13 all other states reserve d ?
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 20 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram status register read (srr) advance status register read (srr) the status register read (srr) is used to read the manufacturer id, revision id, refresh multiplier, width type, and density of the mobile sdram as shown in figure 10. the srr is read via the load mode register command with ba0 = 1 and ba1 = 0. the sequence to perform an srr command is as follows: 1. the sdram must be properly initialized and in the idle or all banks precharged state. 2. issue a load mode register command with ba[1:0] = ?01.? 3. wait t srr; nop or deselect commands are only allowed during the t srr time. 4. issue a read command with all address pins set to ?0.? 5. subsequent commands to the sdram must be issued t src after the srr read com- mand is issued; only nops or deselcts are allowed during t src (see figure 10: ?sta- tus register definition? on page 21). srr output is read with a burst length of 2. srr data is driven to the outputs on the first bit of the burst, with the output being ?d on?t care? on the second bit of the burst. figure 9: srr timing notes: 1. all banks must be idle prior to status register read. 2. nop or deselect commands are required between lmr and read command ( t srr), and between read and next valid command ( t src). 3. cas latency is pre-determined by the programming of the mode register. cl = 3 is shown as an example only. 4. burst length is fixed to 2 for srr regardless of the value programmed by the mode register. 5. the second bit of the data out burst is a ? don?t care. ? c ommand ba0, ba1 c k c k# addre ss read nop nop t0 t1 t2 t3 t4 t5 t 6 t7 don ? t c are nop dq s dq s rr out 4 t rp pre 1 lmr nop 2 nop valid t8 ba0 = 1 ba1 = 0 0 t s rr t s r c c l = 3 3 don ? t c are 5
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 21 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram status register read (srr) advance figure 10: status register definition notes: 1. reserved bits should be set to zero (0) for future compatibility. 2. refresh multiplier is based on the memory device?s on-board temperature sensor. required average periodic refresh interval = t refi * multiplier. stopping the external clock one method of controlling the power efficiency in applications is to throttle the clock that controls the ddr sdram. there are two ways to control the clock: 1. change the clock frequency. 2. stop the clock. the mobile ddr sdram allows the clock to change frequency during operation only if all the timing parameters are met and all refresh requirements are satisfied. s tatus re g ister i/o bus ( c lk l->h e dg e) 97 6 54 3 821 manufa c turer id reserve d revision id refresh rate s 12 dq11 s 11 dq10 s 10 dq9 s 9 dq8 s 8 dq7 s 7 dq 6 s6 dq5 s 5 dq4 s 4 dq3 s 3 dq2 s 2 dq1 s 1 dq0 s 0 10 11 12 s 2 s 1 manufa c turer id reserve d s amsun g infineon elpi d a reserve d reserve d dq14 dq12 s 14 dq31..dq1 6 s 31.. s 1 6 reserve d 1 13 14 31..1 6 0 s 13 s 3 1 11 1 1 10 1 1 01 1 1 00 1 0 11 1 0 10 1 0 01 1 0 00 1 1 11 0 1 10 0 1 01 0 1 00 0 0 11 0 0 10 0 0 01 0 0 00 0 reserve d reserve d win b on d reserve d reserve d reserve d reserve d mi c ron e s mt nvm s 0 wi d th type density dq13 15 dq15 s 15 s6 s 5 revision id the manufa c turer ? s revision num b er starts at ?0000 ? an d in c rements b y ?0001 ? ea c h time a c han g e in the spe c ifi c ation (a c timin g s or feature set), ibi s (pull- up or pull- d own c hara c teristi c s), or pro c ess o cc urs. x xx x 0 00 0 s 4 ... ... ... ... s 10 s 9 refresh multiplier 2 reserve d reserve d 2x 1x reserve d 1 11 1 10 1 01 1 00 0 11 0 10 0 01 0 00 0.25x s 8 s 7 devi c e wi d th 32 b its 1 0 s 11 1 6 b its devi c e type lpddr2 1 0 s 12 lpddr s 10 s 9 density 1 11 1 10 1 01 1 00 0 11 0 10 0 01 0 00 s 8 reserve d reserve d reserve d reserve d 1024m b 512m b 25 6 m b 128m b reserve d
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 22 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram status register read (srr) advance the clock can be stopped altogether if there are no dram operations in progress that would be affected by this change. any dr am operation already in process must be completed before entering clock stop mode; this includes the following timings: t rcd, t rp, t rfc, t mrd, t wr, and all data-out for read bursts. for example, if a write or a read is in progress, the entire data burst must be complete prior to stopping the clock. for reads, a bu rst completion is defined when the read postamble is satisfied. for writes, a burst completion is defined when the write post- amble and t wr or t wtr are satisfied. cke must be held high with ck = low and ck# = high for the full duration of the clock stop mode. one clock cycle and at least one nop or deselect is required after the clock is restarted before a valid command can be issued. figure 11 on page 22 illus- trates the clock stop mode. figure 11: clock stop mode notes: 1. prior to ta1, the device is in clock stop mode. to exit, at least one nop is required before any valid command. 2. any valid command is allowed; device is not in clock suspend mode. exit c lo c k s top mo d e c ke c k c k# c ommand ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop t a 1 t a 2 t b 3 t b 4 don ? t c are a dd ress dq, dq s (hi g h-z) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) enter c lo c k s top mo d e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) c md 2 v ali d c md 2 v ali d nop 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all dram a c tivities must b e c omplete ( ) ( ) ( ) ( )
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 23 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram commands advance commands table 6 and table 7 provide a quick reference of available commands. this is followed by a written description of each command. th ree additional truth tables (table 8 on page 49, table 9 on page 50, and table 10 on page 52) provide cke commands and current/next state information. notes: 1. cke is high for all commands shown except self refresh and deep power-down. 2. all states and sequences not show n are reserved and/or illegal. 3. deselect and nop are functionally interchangeable. 4. ba0?ba1 provide bank address and a0?a12/a13 provide row address. 5. ba0?ba1 provide bank address; a0?a9 provide column address; a10 hi gh enables the auto precharge feature (nonpersistent); a10 lo w disables the auto precharge feature. 6. applies only to read bursts with auto precharge disabl ed; this command is undefined (and should not be used) for read bursts with au to precharge enabled and for write bursts. 7. this command is a burst terminate if cke is high and deep power-down if cke is low. 8. a10 low: ba0?ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0 ? ba1 are ? don?t care. ? 9. this command is auto refresh if cke is high, self refresh if cke is low. 10. internal refresh counter controls ro w addressing; all inputs and i/os are ? don?t care ? except for cke. 11. ba0?ba1 select either the standard mode register or the exte nded mode register (ba0 = 0, ba1 = 0 select the standard mode re gister; ba0 = 0, ba1 = 1 select extended mode register; other combinations of ba0?ba1 are reserved). a0?a12/a13 pr ovide the op-code to be written to the selected mode register. notes: 1. used to mask write data; provided coincident with the corresponding data. 2. all states and sequences not show n are reserved and/or illegal. table 6: truth table ? commands notes 1 and 2 appl y to all commands name (function) cs# ras# cas# we# address notes deselect (nop) hxx x x 3 no operation (nop) lhhh x 3 active (select bank and activate row) l l h h bank/row 4 read (select bank and colu mn, and start read burst) l h l h bank/column 5 write (select bank and column, and start write burst) l h l l bank/column 5 burst terminate or deep power-down (enter deep power-down mode) lhh l x 6, 7 precharge (deactivate row in bank or banks) l l h l code 8 auto refresh (refresh all or single bank) or self refresh (enter self refresh mode) lllh x 9, 10 load mode register (standard or extended mode registers) lll l op-code 11 table 7: dm operation truth table name (function) dm dq notes write enable l valid 1, 2 write inhibit hx1, 2
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 24 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram commands advance deselect the deselect function (cs# high) prevents new commands from being executed by the mobile ddr sdram. operations already in progress are not affected. deep power-down deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the memory array. da ta will not be retained once the device enters deep power down mode. no operation (nop) the no operation (nop) command is used to instruct the s elected mobile ddr sdram to perform a nop. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0?a12/a13. see mode register descriptions in ?register definition? on page 15. the load mode register command can only be issued when all banks are idle, and a subseq uent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8/a9 selects the starting column location. the va lue on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = the most significant column address bit for each configuration) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input da ta appearing on the dqs is written to the memory array subject to the dm input logic le vel appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corr esponding data inputs will be ignored, and a write will not be executed to that byte/column location.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 25 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram commands advance precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. the exception is the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. inpu t a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. othe rwise, ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank . a precharge command will be treated as a nop if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge func- tion described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon co mpletion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each indi- vidual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. this ?earliest valid stage? is determ ined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min), as described for each burst type in ?operations? on page 27. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. burst terminate the burst terminate command is used to tr uncate read bursts with auto precharge disabled. the most recently registered read command prior to the burst terminate command will be truncated, as shown on page 33. the open page that the read was terminated from remains open. auto refresh auto refresh is used during normal op eration of the mobile ddr sdram and is analogous to cas#-before-ras# (cbr) refresh in fpm/edo drams. the auto refresh command is nonpersistent and must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto re fresh command. the 1gb mobile ddr sdram requires auto refresh cycles at an average interval of 7.8125s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refr esh interval is provided. although it is not a jedec requirement, ck e must be active (high) during the auto refresh period to allow for future functional features. the auto refresh period begins when the auto refresh command is registered and ends t rfc later.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 26 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram commands advance self refresh the self refresh command can be used to retain data in the mobile ddr sdram even if the rest of the system is powered down. when in the self refresh mode, the mobile ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command ex cept that cke is disabled (low). all command and address input signals except cke are ?don?t care? during self refresh. see figure 45 on page 72 for details on ente ring and exiting self refresh mode. during self refresh, the device is refreshed as identified in the extended mode register (see pasr setting). the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. once cke is high, the mobile ddr sdram must have nop commands issued for t xsr, in order to complete any internal refresh already in progress. figure 12: mobile dram state diagram power on power applie d dpd s x ref s x mr s refa ref s dpd s a c t c kel c kel c keh c keh pre pre c har g e all b anks mr s emr s deep power down s elf refresh i d le all b anks pre c har g e d row a c tive burst stop read read a automati c se q uen c e c omman d se q uen c e write write write write a write a pre c har g e preall a c tive power d own pre c har g e power d own auto refresh pre write a read a read a pre pre read a read read read b s t
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 27 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance operations bank/row activation before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be ?opene d.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 13. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 13: activating a specific row in a specific bank notes: 1. ba = bank address. ra = row address. reads read burst operations are initiated with a read command, as shown in figure 14 on page 29. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. cs # we# c a s # ra s # c ke a0?a12 ra hi g h ba0, ba1 ba c k c k# don ? t c are
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 28 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance during read bursts, the valid data-out elem ent from the starting column address will be available following the cas latency after the read command. each subsequent data- out element will be valid nominally at the next positive or negative clock edge (for example, at the next crossing of ck and ck#). figure 15 on page 30 shows general timing for each possible cas latency setting. dq s is driven by the mobile ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), the valid data window are depicted in figure 33 on page 46. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 40 on page 68. data from any read burst may be concatenat ed with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be main- tained. the first data element from the new burst follows either the last element of a completed burst or the last desired data elem ent of a longer burst which is being trun- cated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 16 on page 31. a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is sh own for illustration in figure 17 on page 32. full-speed random read accesses within a page (or pages) can be performed as shown in figure 18 on page 32.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 29 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 14: read command notes: 1. ca = column address. ba = bank address. en ap = enable auto precharge. dis ap = disable auto precharge. 2. i = the most significant column ad dress bit for each configuration. cs # we# c a s # ra s # c ke c a a0?a9 a10 ba0,1 hi g h en ap di s ap ba a11?a i 2 c k c k# don ? t c are
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 30 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 15: read burst notes: 1. d out n = data-out from column n . c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 t1n c ommand read nop nop nop nop nop addre ss bank a, c ol n don ? t c are tran s itionin g data dq dq s c l = 2 c ommand read nop nop nop nop nop addre ss bank a, c ol n dq dq s c l = 3 d out n d out n + 1 d out n + 3 d out n + 2 d out n 1 d out n + 1 d out n + 3 d out n + 2
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 31 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 16: consecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t5 t4n t5n c ommand read nop read nop nop nop addre ss bank, c ol n bank, c ol b c ommand read nop read nop nop nop addre ss bank, c ol n bank, c ol b c ommand addre ss don ? t c are tran s itionin g data dq dq s c l = 2 dq dq s c l = 3 d out n 1 d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1 d out b + 3 d out b + 2 d out n d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 32 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 17: nonconsecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). figure 18: random read accesses notes: 1. d out n (or x , b, g ) = data-out from column n ( or column x , column b , column g ). c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c ommand read nop nop nop nop nop addre ss bank, c ol n read bank, c ol b don ? t c are tran s itionin g data dq dq s c l = 2 c l = 2 c ommand read nop nop nop nop nop addre ss bank, c ol n read bank, c ol b dq dq s c l = 3 c l = 3 d out n d out n + 1 d out n + 3 d out n + 2 d out n 1 d out b d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1 d out b + 2 c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c ommand read read read nop nop addre ss bank, c ol n bank, c ol x bank, c ol b bank, c ol x bank, c ol b read bank, c ol g c ommand addre ss c ommand addre ss read read read nop nop bank, c ol n read bank, c ol g don ? t c are tran s itionin g data dq dq s c l = 2 dq dq s c l = 3 d out n 1 d out n + 1 d out x + 1 d out x d out b d out b + 1 d out g + 1 d out g d out n d out n + 1 d out b d out b + 1 d out x + 1 d out x
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 33 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance truncated reads data from any read burst may be truncated with a burst terminate command, as shown in figure 17. the burst terminate latenc y is equal to the read (cas) latency; for example, the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any read burst must be complete d or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 18. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or tr uncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the n -prefetch architecture). this is shown in figure 21 on page 35. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note: part of the row precharge time is hidden du ring the access of the last data elements. figure 19: terminating a read burst notes: 1. dout n = data-out from column n . c k c k# t0 t1 t2 t3 t2n t4 t5 t1n c ommand read b s t 4 nop nop nop nop addre ss bank a , c ol n don ? t c are tran s itionin g data dq dq s c l = 2 c k c k# t0 t1 t2 t3 t2n t4 t5 t3n c ommand read b s t 4 nop nop nop nop addre ss bank a , c ol n dq dq s c l = 3 d out n d out n + 1 d out n 1 d out n + 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 34 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 20: read-to-write notes: 1. d out n = data-out from column n . 2. d in b = data-in from column b . 3. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 4. shown with nominal t ac, t dqsck, and t dqsq. 5. bst = burst terminate comm and; page remains open. 6. cke = high. ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n ck don?t care transitioning data command read bst 5 nop nop nop address bank, col n write bank, col b dm (nom) t dqss dq dqs cl = 2 command read bst 5 nop nop address bank, col n write bank, col b dm (nom) t dqss dq dqs cl = 3 nop d out n d out n + 1 d in b + 1 d in b d out n d out n + 1 d in b+1 d in b+2 d in b+3 d in b
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 35 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 21: read-to-precharge notes: 1. d out n = data-out from column n . 2. bl = 4 or an interrupted burst of 8. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. read-to-precharge equals 2 clocks, which allows 2 data pairs of data-out. 5. a read command with auto pr echarge enabled, provided t ras (min) is met, would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl/2. 6. pre = precharge command; act = active command. ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n command 5 read nop pre nop nop act address bank a , col n bank a , ( a or all ) bank a , row dq dqs cl = 2 t rp read nop pre nop nop act bank a , col n command 5 address bank a , ( a or all ) bank a , row dq dqs cl = 3 t rp don?t care transitioning data d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 d out n + 3 d out n + 2
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 36 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance writes write bursts are initiated with a write command, as shown in figure 22 on page 37. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and th e first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases (for example, t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 23 on page 38 shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain hi gh-z and any additional input data will be ignored. data for any write burst may be concatenat ed with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data elem ent from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 24 on page 38 shows concatenated burs ts of 4. an example of nonconsecutive writes is shown in figure 25 on page 39. full-speed random write accesses within a page or pages can be performed, as shown in figure 26 on page 39. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 27 on page 40. data for any write burst may be truncated by a subsequent read command, as shown in figure 28 on page 41. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 29 on page 42. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 30 on page 43. data for any write burst may be truncated by a subsequent precharge command, as shown in figure 28 on page 41 and figure 32 on page 45. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 28 on page 41 and figure 32 on page 45. after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 37 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 22: write command notes: 1. ca = column address. ba = bank address. en ap = enable auto precharge. dis ap = disable auto precharge. cs # we# c a s # ra s # c ke c a a10 ba0,1 hi g h en ap di s ap ba c k c k# don ? t c are a0?a9 a11, a12
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 38 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 23: write burst notes: 1. d in b = data-in for column b . 2. an uninterrupted burst of 4 is shown. 3. a10 is low with the write comm and (auto precharge is disabled). figure 24: consecutive write-to-write notes: 1. d in b ( n ) = data-in for column b ( n ). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. dq s t d q ss (max) t d q ss (nom) t d q ss (min) t dq ss dm dq c k c k# c ommand write nop nop addre ss bank a , c ol b nop t0 t1 t2 t3 t2n dq s t dq ss dm dq dq s t dq ss dm dq d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 c k c k# c ommand write nop write nop nop addre ss bank, c ol b nop bank, c ol n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq dq s dm don ? t c are tran s itionin g data t dq ss t d q ss (nom) d in b+1 d in b+2 d in b+3 d in n d in n+1 d in n+2 d in n+3 d in b
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 39 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 25: nonconsecutive write-to-write notes: 1. d in b ( n ) = data-in for column b ( n ). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. figure 26: random write cycles notes: 1. d in b ( or x , n , a , g ) = data-in for column b (or x, n, q, g ). 2. b' (or x, n, a, g ) = the next data-in following d in b ( x, n, a, g ) according to the programmed burst order. 3. programmed bl = 2, 4, or 8 in cases shown. 4. each write command may be to any bank. c k c k# c ommand write nop nop nop nop addre ss bank, c ol b write bank, c ol n t0 t1 t2 t3 t2n t4 t5 t4n t1n t5n dq dq s dm t d q ss (nom) t dq ss don ? t c are tran s itionin g data d in b+1 d in b+2 d in b+3 d in b d in n+1 d in n+2 d in n+3 d in n t dq ss (nom) c k c k# c ommand write write write write nop addre ss bank, c ol b bank, c ol x bank, c ol n bank, c ol g write bank, c ol a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq dq s dm don ? t c are tran s itionin g data d in b? d in x d in x? d in b d in n? d in a d in a? d in g d in g ? d in n
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 40 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 27: write-to-read ? uninterrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an uninterrupted burst of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. the read and write commands are to the same device. however, the read and write commands may be to differen t devices, in which case t wtr is not required and the read command could be applied earlier. 5. a10 is low with the write comm and (auto precharge is disabled). t dqss (nom) c k c k# c ommand write nop nop read nop nop addre ss bank a , c ol b bank a , c ol n nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 t 6 n t wtr c l = 2 dq dq s dm t dq ss t dqss (min) c l = 2 dq dq s dm t dq ss t dqss (max) c l = 2 dq dq s dm t dq ss don ? t c are tran s itionin g data t5n d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d out n d out n + 1 d out n d out n + 1 d out n d out n + 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 41 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 28: write-to-read ? interrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an interrupted burst of 4 is show n; two data elements are written. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is required at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs woul d be required at t3 and t3n because the read command would not mask th ese two data elements. t d q ss (nom) c k c k# c ommand write nop nop nop nop nop addre ss bank a, c ol b bank a, c ol n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm t d q ss (min) c l = 3 dq dq s dm t d q ss (max) c l = 3 dq dq s dm don ? t c are tran s itionin g data t dq ss t dq ss t dq ss d in b+1 d in b d in b+1 d in b d in b+1 d in b d out n d out n + 1 d out n d out n + 1 d out n d out n + 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 42 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 29: write-to-read ? odd number of data, interrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an interrupted burst of 4 is shown; one data elements is written, three are masked. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is required at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs would be required at t2n, t3, and t3n because the read command would not mask these three data elements. t d q ss (nom) c k c k# c ommand write nop nop nop nop nop addre ss bank a , c ol b bank a , c ol b read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm t d q ss (min) c l = 3 dq dq s dm t d q ss (max) c l = 3 dq dq s dm don ? t c are tran s itionin g data t dq ss t dq ss t dq ss d in b d out n d out n + 1 d out n d out n + 1 d out n d out n + 1 d in b d in b
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 43 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 30: write-to-precharge ? uninterrupting notes: 1. pre = pr echarge command. 2. d in b = data-in for column b . 3. an unterrupted burst 4 of is shown. 4. a10 is low with the write comm and (auto precharge is disabled). 5. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 6. the precharge and write commands are to the same device. however, the precharge and write commands may be to di fferent devices; in this case, t wr is not required and the precharge command coul d be applied earlier. c k c k# c ommand write nop nop nop nop addre ss bank a , c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm dq dq s dm dq dq s dm don ? t c are tran s itionin g d a t a t wr pre 1 t d q ss (nom) t d q ss (min) t d q ss (max) t dq ss t dq ss t dq ss d in b 2 d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 44 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 31: write-to-precharge ? interrupting notes: 1. pre = pr echarge command. 2. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 3. d in b = data-in for column b . 4. an interrupted burst of 8 is show n; two data elements are written. 5. a10 is low with the write comm and (auto precharge is disabled). 6. dqs is required at t4 and t4n to register dm. 7. if the burst of 4 is used, dqs and dm are not required at t3, t3n, t4, and t4n. t d q ss (nom) ck ck# command write nop nop nop nop address bank a , col b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 dq dqs dm t dqss t d q ss (min) dq dqs dm t dqss t d q ss (max) dq dqs dm t dqss don ? t c are tran s itionin g data t wr 2 pre 1 t4n t3n d in b 3 d in b + 1 d in b d in b + 1 d in b d in b + 1
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 45 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram operations advance figure 32: write-to-precharge ? odd number of data, interrupting notes: 1. pre = pr echarge command. 2. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 3. d in b = data-in for column b . 4. an interrupted burst of 8 is sh own; one data el ement is written. 5. dqs is required at t4 and t4n to register dm. 6. if the burst of 4 is used, dqs and dm are not required at t3, t3n, t4, and t4n. 7. a10 is low with the write comm and (auto precharge is disabled). t d q ss (nom) c k c k# c ommand write nop nop nop nop addre ss bank a , c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm t dq ss t d q ss (min) dq dq s dm t dq ss t d q ss (max) dq dq s dm t dq ss don ? t c are tran s itionin g d a t a d in b d in b d in b 3 t wr 2 pre 1 t4n t3n
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 46 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram power-down advance precharge command the precharge command (figure 33) is used to deactivate the open row in a partic- ular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged (a10 = low), inputs ba0, ba1 select the bank. when all banks are to be precharged (a10 = high), inputs ba0, ba1 are treated as a ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 33: precharge command notes: 1. ba = bank address. all = a10 high, all banks to be precharged, ba1, ba0 are ? don?t care. ? single = a10 low, only bank selected by ba1 and ba0 will be precharged. 2. i = the most significant column ad dress bit for each configuration. power-down power-down (figure 33) is entered when cke is registered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power- down occurs when there is a row active in an y bank, this mode is referred to as active power-down. entering power-down deactivate s all input and output buffers, including ck and ck# and excluding cke. exiting power-down requires the device to be at the same voltage as when it entered powe r-down and receiving a stable clock. note: the power-down duration is limited by the refresh requirements of the device. while in power-down, cke low must be maintained at the inputs of the mobile ddr sdram, while all other input signals are ?don?t care.? the power-down state is synchro- nously exited when cke is registered high (in conjunction with a nop or deselect cs # we# c a s # ra s # c ke a10 ba0, ba1 hi g h all s in g le ba c k c k# don ? t c are a0?a9, a11-a i 2
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 47 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance command). nops or deselect commands must be maintained on the command bus until t xp is satisfied. see figure 43 on page 70 for a detailed illustration of the power- down command. figure 34: power-down command (in active or precharge modes) deep power-down (dpd) deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the memory array. da ta will not be retained once the device enters deep power-down mode. before entering dpd mode the dram must be in all banks idle state with no activity on the data bus ( t rp time must be met). this mode is entered by holding cs# and we# low with ras# and cas# high at the rising edge of the clock while cke is low. cke must be held low to maintain dpd mode. the clock mu st be stable prior to exiting dpd mode. this mode is exited by asserting cke high with either a nop or deselect command present on the command bus. upon exiting dp d mode, 200s of valid clocks with either nops or deslect commands present on the command bus are required; a precharge all command and a full dram initialization sequence are required. cs # ra s #, c a s #, we# c ke ba0,1 c k c k# don ? t c are a0?a12 ra s #, c a s #, we# cs # ba0?ba1 or
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 48 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance figure 35: deep power-down command figure 36: deep power-down notes: 1. clock must be stable prior to cke going high. 2. dpd = deep power-down mode command. 3. upon exit of deep power-down mode, a precharge all command must be issued fol- lowed by the initialization sequence (page 14). cs # we# c a s # ra s # c ke a0?a12 ba0, ba1 c k c k# don ? t c are t i s all b anks i d le with no a c tivity on the d ata b us exit d eep power- d own mo d e enter d eep power- d own mo d e c ke c k c k# c ommand dpd 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop vail d 3 t0 t1 t2 ta0 1 ta1 ta2 nop don ? t c are t c ke ta3 t = 200s
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 49 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance notes: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command regi stered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not sh own are illegal or reserved. 5. t cke pertains. 6. deselect or nop commands should be issued on any clock edges occurring during the t xp period. 7. the clock must toggle at least one time during the t xp period. 8. deselect or nop commands should be issued on any clock edges occurring du ring the t xsr period. 9. the clock must toggle at least one time during the t xsr period. 10. 200 s of valid clocks and nops (or deselects) commands are required before any other valid command is allowed. 11. upon exiting deep power-down mode and after the 200 s, a precharge all command is required, followed by the standa rd initialization sequence. table 8: truth table ? cke notes: 1?5 cke n-1 cke n current state command n action n notes l l active power-down x maintain active power-down l l deep power-down x maintain deep power-down l l (precharge) power-down x mai ntain (prechar ge) power-down l l self refresh x maintain self refresh l h active power-down deselect or nop exit active power-down 6, 7 l h deep power-down dese lect or nop exit deep power-down 10, 11 l h (precharge) power-down deselect or nop exit (precharge) power-down 6, 7 l h self refresh deselect or nop exit self refresh 8, 9 h l bank(s) active deselect or nop active power-down entry h l all banks idle burst terminate deep power-down entry h l all banks idle deselect or no p (precharge) power-down entry h l all banks idle auto refresh self refresh entry h h see table 10 on page 52 h h see table 10 on page 52
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 50 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance notes: 1. this table applies when cke n-1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh), after t xp has been met (if the previous state was power down), or 200 s if the previous state was deep power-down). 2. this table is bank-specific, except where note d (for example, the current state is for a spe- cific bank and the commands shown are those allo wed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to any other bank are determined by that bank?s current state. table 9: truth table ? current state bank n - command to bank n notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 row active lhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10, 12 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10, 11 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8, 11 lhhl burst terminate 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated wi th auto precharge disabled and has not yet terminated or been terminated. write: a write burst has been initiated wi th auto precharge disabled and has not yet terminated or been terminated. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto- precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto- precharge enabled: starts with registration of a wr ite command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 51 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance 5. the following states must not be interrupt ed by any executable command; deselect or nop commands must be applied on each pos itive clock edge during these states. 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; requires that all bank s are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects th e most recent read or write burst, regard- less of bank. 10. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after th e completion of the read burst; otherwise, a burst terminate must be used to end th e read burst prior to asserting a write command. refreshing: starts with registration of an auto refresh comm and and ends when t rfc is met. once t rfc is met, the ddr sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the mobile ddr sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 52 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance notes: 1. this table applies when cke n -1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh) or after t xp has been met (if the previous state was power-down). 2. this table describes alternate bank operatio n, except where noted (for example, the cur- rent state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that given co mmand is allowable). exceptions are covered in the notes below. 3. current state definitions: 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then fo llowed with the earl iest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. table 10: truth table ? current state bank n ? command to bank m notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle xxxx any command allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8 lhl l write (select column and start new write burst) 7 llhl precharge read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 3a lhl l write (select column and start write burst) 7, 9, 3a llhl precharge write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 3a lhl l write (select column and start new write burst) 7, 3a llhl precharge idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated wi th auto precharge disabled and has not yet terminated or been terminated. write: a write burst has been initiated wi th auto precharge disabled and has not yet terminated or been terminated.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 53 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram deep power-down (dpd) advance this device supports concurrent auto precha rge such that when a read with auto pre- charge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. in either case, all other related limita tions apply (e.g., con- tention between read data and write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled to a command to a different ba nk is summarized below. cl ru = cl rounded up to the next integer. 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 8. requires appropriate dm masking. 9. a write command may be appl ied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. from command to c o m m a n d minimum delay (with concurrent auto precharge) write w/ap read or read w/ap write or write w/ap precharge active [1 + (bl/2)] t ck + t wtr (bl/2) t ck 1 t ck 1 t ck read w/ap read or read w/ap write or write w/ap precharge active (bl/2) x t ck [cl ru + (bl/2)] t ck 1 t ck 1 t ck
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 54 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance electrical specifications table 11: operating temperature parameter symbol min max unit notes operating temperature t a (commercial 0+70c t a (industrial) it ?40 +85 c storage temperature (plastic) t stg ?55 +150 c table 12: ac/dc electrical characteristics and operating conditions notes: 1?5; notes appear on page 61 v dd /v dd q = 1.70?1.95v parameter/condition symbol min max unit notes supply voltage v dd 1.70 1.95 v 32, 34 i/o supply voltage v dd q 1.70 1.95 v 32, 34 address and command inputs input voltage high v ih 0.8 v dd qv dd q + 0.3 v 25, 33 input voltage low v il ?0.3 0.2 v dd q v 25, 33 clock inputs (ck, ck#) dc input voltage v in ?0.3 v dd q + 0.3 v27 dc input differ ential voltage v id ( dc ) 0.4 v dd qv dd q + 0.6 v8, 27 ac input differ ential voltage v id ( ac ) 0.6 v dd qv dd q + 0.6 v8, 27 ac differential crossing voltage v ix 0.4 v dd q 0.6 v dd q v9, 27 data inputs dc input high voltage v ih ( dc ) 0.7 v dd qv dd q + 0.3 v 25, 28, 33 ac input high voltage v ih ( ac ) 0.8 v dd qv dd q + 0.3 v 25, 28, 33 dc input low voltage v il ( dc ) ?0.3 0.3 v dd q v 25, 28, 33 ac input low voltage v il ( ac ) ?0.3 0.2 v dd q 25, 28, 33 data outputs dc output high voltage: logic 1 (i oh = ?0.1ma) v oh 0.9 v dd q ?v dc output low voltage: logic 0 (i ol = 0.1ma) v ol ?0.1 v dd qv leakage current input leakage current any input 0v v in v dd (all other pins not under test = 0v) i i ?1 1 a output leakage current (dqs are disabled; 0v v out v dd q) i oz ?5 5 a
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 55 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance table 13: capacitance (x16, x32) notes: 13; notes appear on page 61 parameter symbol min max unit notes delta input/output capa citance: dqs, dqs, dm dc i 0 ?2.0pf21 delta input capacitance: command and address dc i 1 ?2.25pf26 delta input capacitance: ck, ck# dc i 2 ?0.5pf26 input/output capacitance: dqs, dqs, dm c i 0 2.0 5.0 pf input capacitance: command and address c i 1 2.0 5.0 pf input capacitance: ck, ck# c i 2 2.0 3.5 pf input capacitance: cs#, cke c i 3 2.0 5.0 pf
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 56 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance table 14: i dd specifications and conditions (x16) notes: 1?5, 10, 12, 14; no tes appear on page 61; v dd /v dd q = 1.70?1.95v parameter/condition symbol max unit notes -6 -75 operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every two clock cycles; data bus inputs are stable i dd 0 95 90 ma 19 precharge power-down standby current: all banks idle, cke is low; cs is high, t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2p 600 600 a 20, 29, 44 precharge power-down standby current with clock stopped: all banks idle; cke is low; cs is high, ck = low, ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 2ps 600 600 a 20, 29, 44 precharge nonpower-down standby current: all banks idle cke = high; cs = high; t ck = t ck (min); address and control inputs are swit ching; data bus inputs are stable i dd 2n 36 30 ma 36 precharge nonpower-down standby current: clock stopped all banks idle, cke = high; cs = high; ck = low, ck# = high address and control inputs are swit ching; data bus inputs are stable i dd 2ns 24 18 ma 36 active power-down standby current: one bank active, cke = low; cs = high; t ck = t ck (min); address and control inputs are swit ching; data bus inputs are stable i dd 3p 3.6 3.6 ma 20, 29 active power-down standby current: clock stopped one bank active, cke = low; cs = high; ck = low; ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 3ps 3.6 3.6 ma 20, 29 active nonpower-down standby: one bank active, cke = high; cs = high; t ck = t ck (min); address and control inputs are swit ching; data bus inputs are stable i dd 3n 36 30 ma 19 active nonpower-down standby: clock stopped one bank active, cke = high; cs = high; ck = low; ck# = high address and control inputs are swit ching; data bus inputs are stable i dd 3ns 30 24 ma 19 operating burst read: one bank active; bl = 4; t ck = t ck (min); continuous read bursts; i out = 0ma; address inputs are switching every two clock cycles; 50% data changing each burst i dd 4r 140 130 ma 19 operating burst write: one bank active; bl = 4; t ck = t ck (min); contin uous write bursts; address inputs are switching; 50% data changing each burst i dd 4w 140 130 ma 19 auto refresh: burst refresh; cke = high address and control inputs are switching; data bus inputs are stable t rfc = t rfc (min) i dd 5 190 175 ma 37 t rfc = t refi i dd 5a 15 14 ma 24, 37 deep power-down current: address and control ba lls are stable; data bus inputs are stable i dd 8 10 a 44, 45
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 57 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance table 15: i dd specifications and conditions (x32) notes: 1?5, 10, 12, 14; notes appear on pages 61 v dd /v dd q = 1.70?1.95v parameter/condition symbol max unit notes -6 -75 operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every two clock cycles; data bus inputs are stable i dd 0 110 105 ma 19 precharge power-down standby current: all banks idle, cke is low; cs is high, t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2p 600 600 a 20, 29, 44 precharge power-down standby current with clock stopped: all banks idle; cke is low; cs is high, ck = low, ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 2ps 600 600 a 20, 29, 44 precharge nonpower-down standby current: all banks idle cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 2n 36 30 ma 36 precharge nonpower-down standby current: clock stopped all banks idle, cke = high; cs = high; ck = low, ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 2ns 24 18 ma 36 active power-down standby current: one bank active, cke = low; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3p 3.6 3.6 ma 20, 29 active power-down standby current: clock stopped one bank active, cke = low; cs = high; ck = low; ck# = high; address and control inputs are swit ching; data bus inputs are stable i dd 3ps 3.6 3.6 ma 20, 29 active nonpower-down standby: one bank active, cke = high; cs = high; t ck = t ck (min); address and control inputs are switching; data bus inputs are stable i dd 3n 36 30 ma 19 active nonpower-down standby: clock stopped one bank active, cke = high; cs = high; ck = low; ck# = high address and control inputs are swit ching; data bus inputs are stable i dd 3ns 30 24 ma 19 operating burst read: one bank active; bl = 4; cl = 3; t ck = t ck (min); continuous read bursts; i out = 0ma; address inputs are switching every two clock cycles; 50% data ch anging each burst i dd 4r 140 130 ma 19 operating burst write: one bank active; bl = 4; t ck = t ck (min); contin uous write bursts; address inputs are switching; 50% data changing each burst i dd 4w 160 140 ma 19 auto refresh: burst refresh; cke = high; address and control inputs are switching; da ta bus inputs are stable t rfc = t rfc (min) i dd 5 190 175 ma 37 t rfc = t refi i dd 5a 15 14 ma 24, 37 deep power-down current: address and control pins are stable; data bus inputs are stable i dd 8 10 10 a 44, 45
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 58 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance figure 37: typical self refresh current vs. temperature table 16: i dd 6 specifications and conditions (x32) notes: 1?5, 10?12, 14; no tes appear on pages 61; v dd /v dd q = 1.70?1.95v parameter/condition symbol max -75/-8 units self refresh cke = low; t ck = t ck (min); address and control inputs are stable; data bus inputs are stable full array, 85c i dd 6a 900 a full array, 70c i dd 6b 720 a full array, 45c i dd 6c 360 a full array, 15c i dd 6d 270 a half array, 85c i dd 6a 585 a half array, 70c i dd 6b 495 a half array, 45c i dd 6c 315 a half array, 15c i dd 6d 225 a 1/4 array, 85c i dd 6a 405 a 1/4 array, 70c i dd 6b 315 a 1/4 array, 45c i dd 6c 225 a 1/4array, 15c i dd 6d 180 a 1/8 array, 85c i dd 6a 360 a 1/8 array, 70c i dd 6b 315 a 1/8 array, 45c i dd 6c 180 a 1/8 array, 15c i dd 6d 158 a 1/16 array, 85c i dd 6a 315 a 1/16 array, 70c i dd 6b 270 a 1/16 array, 45c i dd 6c 180 a 1/16 array, 15c i dd 6d 158 a tbd
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 59 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance table 17: electrical characteristics and recommended ac operating conditions notes: 1?6, 27; notes appear on pages 61 v dd /v dd q = 1.70?1.95v parameter symbol -6 -75 unit notes min max min max access window of dqs from ck/ck# cl = 3 t ac 2.0 5.5 2.0 6.0 ns 7 cl = 2 t ac 2.0 6.5 2.0 6.5 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 t ck clock cycle time cl = 3 t ck(3) 6 ? 7.5 ? ns 7 cl = 2 t ck(2) 12 ? 12 ? ns minimum t cke high/low time t cke 1 ? 1 ? t ck auto precharge write recovery + precharge time t dal???? 40 dq and dm input hold time relative to dqs t dh 0.5 ? 0.75 ? ns 23, 28, 39 dq and dm input setup time relative to dqs t ds 0.5 ? 0.75 ? ns dq and dm input pulse width (for each input) t dipw 2.1 ? 2.2 ? ns 41 access window of dqs from ck/ck# cl = 3 t dqsck 2.0 5.5 2.0 6.0 ns 7 cl = 2 t dqsck 2.0 6.5 2.0 6.5 ns dqs input high pulse width t dqsh 0.35 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.35 0.6 0.4 0.6 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.45 ? 0.6 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising ? setup time t dss 0.2 ? 0.2 ? t ck dqs falling edge from ck rising ? hold time t dsh 0.2 ? 0.2 ? t ck data valid output window (dvw) n/a t qh - t dqsq t qh - t dqsq ns 22 half-clock period t hp t ch, t cl ? t ch, t cl ? ns 30 data?out high-z window from ck/ck# cl = 3 t hz ? 5.5 ? 6.0 ns 7, 15, 35, 36 cl = 2 ?6.5?6.5 data-out low-z window from ck/ck# t lz 1.0 ? 1.0 ? ns 15, 36 address and control input hold time (fast slew rate) t ih f 1.1 ? 1.3 ? ns 14, 39 address and control input setup time (fast slew rate) t is f 1.1 ? 1.3 ? ns 14, 39 address and control input hold time (slow slew rate) t ih s 1.2 ? 1.5 ? ns 14, 39 address and control input setup time (slow slew rate) t is s 1.2 ? 1.5 ? ns 14, 39 address and control input pulse width t ipw 2.7 ? 3.0 ? ns 41 load mode register command cycle time t mrd 2 ? 2 ? t ck dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ? t hp - t qhs ? ns 22, 23 data hold skew factor t qhs ? 0.65 ? 0.75 ns active-to-precharge command t ras 4270,0004570,000ns31 active-to-active/act ive-to-auto refresh command period t rc 60 ? 75 ? ns auto refresh command period t rfc 140 ? 140 ? ns 37
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 60 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram electrical specifications advance active to read or write delay t rcd 18 22.5 ns refresh period t ref ? 64 ? 64 ms average periodic refresh interval t refi?7.8?7.8s20 precharge command period t rp 18 ? 22.5 ? ns dqs read preamble cl = 2 t rpre(2) 0.5 1.1 0.5 1.1 t ck dqs read preamble cl = 3 t rpre(3) 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 12 ? 15 ? ns read of srr to next valid command t src cl + 1 ? cl + 1 ? t ck srr to read t srr 2 ? 2 ? t ck dqs write preamble t wpre 0.25 ? 0.25 ? t ck dqs write preamble setup time t wpres 0 ? 0 ? ns 17, 18 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 16 write recovery time t wr 15 ? 15 ? ns 46 internal write to read command delay t wtr 1 ? 1 ? t ck exit self refresh to first valid command t xsr 140 ? 140 ? ns 42 exit power-down mode to first valid command t xp1?1? t ck 43 table 17: electrical characteristics and recomm ended ac operating conditions (continued) notes: 1?6, 27; notes appear on pages 61 v dd /v dd q = 1.70?1.95v parameter symbol -6 -75 unit notes min max min max
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 61 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram notes advance notes 1. all voltages referenced to v ss . 2. all parameters assume proper device initialization. 3. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. outputs measured with equivalent load; transmission line delay is assumed to be very small: 5. timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v dd q/2 (or to the crossing point for ck/ck#). the output timing refere nce voltage level is v dd q/2. 6. all ac timings assume an input slew rate of 1 v/ns. 7. cas latency definition: with cl = 2 the first data element is valid at ( t ck + t ac) after the clock at which the read command was re gistered, for cl = 3 the first data ele- ment is valid at (2 t ck + t ac) after the first clock at which the read command was registered. 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 10. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 3 with the outputs open. 11. enables on-die refresh and address counters. 12. i dd specifications are tested after the device is properly initialized and values are averaged at the defined cycle rate. 13. this parameter is sampled. v dd /v dd q = 1.70?1.95v, f = 100 mhz, t a = 25c, v out ( dc ) = v dd q/2, v out (peak-to-peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. fast command/addres s input slew rate 1 v/ns. slow command/ address input slew rate 0.5 v/ns. if the slew rate is less than 0.5 v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduct ion in slew rate from the 0.5 v/ns. t ih remains constant. if the slew rate exce eds 4.5 v/ns, functionality is uncertain. 15. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 16. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, bu t system performance (bus turnaround) will degrade accordingly. i/o 20 pf i/o 10 pf full-drive strength half-drive strength 50 50
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 62 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram notes advance 17. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 18. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 19. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measure- ments is the largest multiple of t ck that meets the maximum absolute value for t ras. 20. the refresh period equals 64ms. this eq uates to an average refresh rate of 7.8125s. 21. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t hp ? t qhs). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. 23. referenced to each output group: for x16, ldqs with dq0?dq7; and udqs with dq8?dq15. for x32, dqs0 with dq0?dq7; dq s1 with dq8?dq15; dqs2 with dq16? dq23; and dqs3 with dq24?dq31. 24. this limit is actually a nominal value and does not result in a fail. cke is high during refresh command period ( t rfc [min]) else cke is low (for example, during standby). 25. to maintain a valid level, the transitioning edge of the input must: sustain a constant slew rate from the curren t ac level through to the target ac level, v il ( ac ) or v ih ( ac ). 25a. reach at least the target ac level. 25b. after the ac target level is reached, co ntinue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 26. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 27. ck and ck# input slew rate must be 1 v/ns (2 v/ns if measured differentially). 28. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/ dm/dqs slew rate is less than 0.5 v/ns, timi ng must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncertain. 29. v dd must not vary more than 4% if cke is not active while any bank is active. 30. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the intern al precharge command being issued. 32. any positive glitch must be less than 1/ 3 of the clock cycle and not more than +200mv or 2.0v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either ?150mv or 1.6v, whichever is more positive. 33. v ih overshoot: v ih (max) = v dd q + 1.0v for a pulse width 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = ?1.0v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 34. v dd and v dd q must track each other and v dd q must be less than or equal to v dd . 35. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 36. i dd 2n specifies dq, dqs, and dm to be driven to a valid high or low logic level.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 63 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram notes advance 37. cke must be active (high) during the entire time a refresh command is executed. from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t rfc later. 38. the values for i dd 6 at 70c, 45c, and 15c are appr oximate only and are not tested. 39. the transition time for in put signals (cas#, cke, cs#, dm, dq, dqs, ras#, we#, and addresses) are me asured between v il ( dc ) to v ih ( ac ) for rising input signals and v ih ( dc ) to v il ( ac ) for falling input signals. 40. t dal = ( t wr/ t ck) + ( t rp/ t ck): for each term, if not already an integer, round to the next higher integer. 41. these parameters guarantee device timi ng but are not tested on each device. 42. clock must be toggled a minimum of two times during this period. 43. clock must be toggled a minimum of one time during this period. 44. measurement is taken 500ms after entering in to this operating mode to allow settling time for the tester. 45. typical values at 25 c, not a maximum value. 46. at least one clock cycle is required during t wr time when in auto precharge mode.
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 64 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram notes advance table 18: target normal output drive characteristics (full-drive strength) the above characteristics are specified unde r best and worst process variation/conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 2.80 18.53 ?2.80 ?18.53 0.20 5.60 26.80 ?5.60 ?26.80 0.30 8.40 32.80 ?8.40 ?32.80 0.40 11.20 37.05 ?11.20 ?37.05 0.50 14.00 40.00 ?14.00 ?40.00 0.60 16.80 42.50 ?16.80 ?42.50 0.70 19.60 44.57 ?19.60 ?44.57 0.80 22.40 46.50 ?22.40 ?46.50 0.85 23.80 47.48 ?23.80 ?47.48 0.90 23.80 48.50 ?23.80 ?48.50 0.95 23.80 49.40 ?23.80 ?49.40 1.00 23.80 50.05 ?23.80 ?50.05 1.10 23.80 51.35 ?23.80 ?51.35 1.20 23.80 52.65 ?23.80 ?52.65 1.30 23.80 53.95 ?23.80 ?53.95 1.40 23.80 55.25 ?23.80 ?55.25 1.50 23.80 56.55 ?23.80 ?56.55 1.60 23.80 57.85 ?23.80 ?57.85 1.70 23.80 59.15 ?23.80 ?59.15 1.80 ? 60.45 ? ?60.45 1.90 ? 61.75 ? ?61.75
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 65 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram notes advance table 19: target reduced output drive characteristics (one-half drive strength) the above characteristics are specified unde r best and worst process variation/conditions voltage (v) pull-down current (ma) pull-up current (ma) min max min max 0.00 0.00 0.00 0.00 0.00 0.10 1.27 8.42 ?1.27 ?8.42 0.20 2.55 12.30 ?2.55 ?12.30 0.30 3.82 14.95 ?3.82 ?14.95 0.40 5.09 16.84 ?5.09 ?16.84 0.50 6.36 18.20 ?6.36 ?18.20 0.60 7.64 19.30 ?7.64 ?19.30 0.70 8.91 20.30 ?8.91 ?20.30 0.80 10.16 21.20 ?10.16 ?21.20 0.85 10.80 21.60 ?10.80 ?21.60 0.90 10.80 22.00 ?10.80 ?22.00 0.95 10.80 22.45 ?10.80 ?22.45 1.00 10.80 22.73 ?10.80 ?22.73 1.10 10.80 23.21 ?10.80 ?23.21 1.20 10.80 23.67 ?10.80 ?23.67 1.30 10.80 24.14 ?10.80 ?24.14 1.40 10.80 24.61 ?10.80 ?24.61 1.50 10.80 25.08 ?10.80 ?25.08 1.60 10.80 25.54 ?10.80 ?25.54 1.70 10.80 26.01 ?10.80 ?26.01 1.80 ? 26.48 ? ?26.48 1.90 ? 26.95 ? ?26.95
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 66 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance timing diagrams figure 38: data output timing ? t dqsq, t qh, and data valid window (x16) notes: 1. dq transitioning after dqs transitions define the t dqsq window. ldqs defines the lower byte and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq 6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived for each dqs transitions and is defined as t qh - t dqsq. 7. dq8, dq9, dq10, dq11, dq 12, dq13, dq14, or dq15. dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldqs 1 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq0 ? dq7 and ldqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs 1 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8 ? dq15 and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 67 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 39: data output timing ? t dqsq, t qh, and data valid window (x32) notes: 1. dq transitioning af ter dqs transition define t dqsq window. ldqs defines the lower byte and udqs defines the upper byte. 2. byte 0 is dq0...7; byte 1 is dq8...15; byte 2 is dq16...23; byte 3 is dq24...31. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 3. t qh is derived from t hp: t qh = t hp - t qhs. 4. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 5. the data valid window is derive d for each dqs transition and is t qh - t dqsq. dq (last d ata vali d ) dq dq dq dq dq dq dq s 0/dq s 1/dq s 2/dq s 3 dq (last d ata vali d ) dq (first d ata no lon g er vali d ) dq (first d ata no lon g er vali d ) dq0?dq7 an d ldq s , c olle c tively 5 c k c k# byte 0 byte 1 byte 2 byte 3 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow t1 t2 t2n t3 t3n t4 t hp 5 t dq s q 3t dq s q 3t dq s q 3t dq s q 3 t2 t2n t3 t3n t2 t2n t3 t3n t2 t2n t3 t3n t qh 4t qh 4t qh 4 t hp 5t hp 5t hp 5t hp 5t hp 5
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 68 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 40: data output timing ? t ac and t dqsck notes: 1. dq transitioning af ter dqs transition define t dqsq window. 2. all dq must transition by t dqsq after dqs transiti ons, regardless of t ac. 3. t ac is the dq output window relative to ck and is the ? long term ? component of dq skew. 4. shown with cl = 3. figure 41: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. for x16, ldqs controls the lower byte; udqs controls the upper byte. 5. for x32, dqs0 contro ls dq[7:0], dqs1 controls dq[15:8], dqs2 controls dq[23:16], and dqs3 controls dq[31:24]. 6. for x16, ldm controls the lower byte; udm controls the upper byte. 7. for x32, dm0 cont rols dq[7:0], dm1 controls dq[15:8] , dm2 controls dq [23:16], and dm3 controls dq[31:24]. ck ck# dqs, or ldqs/udqs 1 t0 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 t rpst t rpre t hz (max) command nop nop nop nop t dqsck (max) nop t dqsck (max) all dq values, collectively 2 t3 t2n t3n t4n t5n t4 t5 t ac (max) cl = 3 nop read t2 t dqss t dqsh t wpst t dh t ds t dqsl t dss 2t dsh 1 t dsh 1t dss 2 ck ck# t0 3 t1 t1n t2 t2n t3 d in b don ? t c are tran s itionin g data t wpre t wpres dqs 4 dq 5 dm 6
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 69 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 42: initialize and load mode registers notes: 1. pre = precharge command; lmr = load mode register command; ar = auto refresh command; act = active co mmand; ra = row address; ba = bank address. 2. nop or deselect commands ar e required for at least 200s. 3. other valid commands are possible. 4. nops or deselects are required during this time. cke lvcmos high level dq bank address (ba0, ba1) load standard mode register load extended mode register t mrd 4 t mrd 4 t rfc 4 t rfc 4 power-up: v dd and ck stable t = 200s high-z dm dqs high-z addresses ra a10 ra ck ck# v dd v dd q t ch t cl t ck command 1 lmr nop lmr ar t is t ih ba0 = l, ba1 = l ba0 = l, ba1 = h code code t is t ih t is t ih t is t ih t is t ih code code pre all banks t0 t1 ta0 tb0 tc0 td0 te0 tf0 don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 2 ar act ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 70 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 43: power-down mode (active or precharge) notes: 1. if this command is a precharge (or if the device is already in th e idle state), then the power-down mode shown is precharge power-down . if this command is an active (or if at least one row is already active ), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. 3. there must be at least one clock pulse during t xp time. 4. t cke applies if cke goes low at ta2 (entering power-down); t xp applies if cke remains high at ta2 (exit power-down). ck ck# command valid 1 nop address cke dq dm dqs t ck t ch t cl t is t is t ih t is t is t ih t ih enter 2 power-down mode exit 3 power-down mode must not exceed refresh device limits ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 ta1 ta2 t2 nop don?t care ( ) ( ) ( ) ( ) valid tb1 t xp 4 t cke 4 t cke valid no read/write a cc ess in pro g ress valid
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 71 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 44: auto refresh mode notes: 1. pre = precharge; act = ac tive; ar = auto refresh; ra = row address; ba = bank address. 2. nop commands are shown for ease of illustra tion; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. nop or command inhibit are the on ly commands allowed until after t rfc time; cke must be active during cloc k positive transitions. 4. ? don?t care ? if a10 is high at this point; a10 must be high if more than one bank is active (for example, must precharge all active banks). 5. dm, dq, and dqs signals are all ? don?t care ? /high-z for operations shown. 6. the second auto refresh is not required and is only shown as an example of two back-to- back auto refresh commands. 7. i = the most significant column ad dress bit for each configuration. c k c k# c ommand 1 nop 2 v ali d v ali d nop 2 nop 2 pre ra a0?a9, a11?a i 1,7 a10 1 ba0, ba1 1 bank(s) 4 ba ar nop 2, 3 ar 6 nop 2, 3 a c t nop 2 one bank all bank s t c k t c h t c l t i s t i s t ih t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 5 dm 5 dq s 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rf c 6 t rp t rf c t0 t1 t2 t3 t4 t a 0 t b 0 t a 1 t b 1 t b 2 don ? t c are ) ) ( ) ( )
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 72 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 45: self refresh mode notes: 1. clock must be stable, cyclin g within specifications by ta0, before exiting self refresh mode. 2. device must be in the all banks idle sta te prior to entering self refresh mode. 3. nops or deselect are required for t xsr time with at least two clock pulses. 4. ar = auto refresh command. 5. cke must remain low to remain in self refresh. c k 1 c k# c ommand 4 nop ar addre ss c ke 1 valid dq dm dq s valid nop t rp 2 t c h t c l t c k t i s t x s r 3 t i s t ih t i s t i s t ih t ih t i s enter s elf refresh mo d e exit s elf refresh mo d e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t b 0 ta1 ( ) ( ) ( ) ( ) don ? t c are ( ) ( ) ( ) ( ) ta0 1 ( ) ( )
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 73 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 46: bank read ? without auto precharge notes: 1. d out n = data out from column n. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the precharge command can only be applied at t5 if t ras minimum is met. 8. refer to figure 38 on page 66 and figure 39 on page 67 for dqs and dq timing details. 9. i = the most significant column ad dress bit for each configuration. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t ih t is t ih t is t ih t is t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac (min) and t dqsck (min) case 2: t ac ( max) and t dqsck ( max) dq 1 dqs t hz ( max) nop 6 nop 6 command 5 3 act ra ra col n read 2 bank x ra ra ra bank x act bank x nop 5 nop 6 nop 6 don?t care transitioning data a0?a9 a11?a i 9 pre 7 bank x 4 t dqsck (min) t lz (min) t rpst t rpre t dqsck (max) t rpre t rpst t ac ( max) all banks one bank t ac (min) cl = 2 t hz (min) t lz ( max) d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 74 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 47: bank read ? with auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. enable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. refer to figure 38 on page 66 and figure 39 on page 67 for detailed dqs and dq timing. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t r c t rp c l = 2 dm t0 t1 t2 t3 t4 t5 t5n t 6 n t 6 t7 t8 dq 1 dq s c ase 1: t a c ( min) an d t dq sc k ( min) c ase 2: t a c ( max) an d t dq sc k ( max) dq 1 dq s t hz ( max) nop 6 nop 6 c ommand 5 3 a c t ra ra c ol n read 2 bank x ra ra ra bank x a c t bank x nop 6 nop 6 nop 6 don ? t c are tran s itionin g data a0?a9 a11, a12 nop 6 t dq sc k ( min) t lz ( min) t rpre t rp s t t hz ( min) t dq sc k ( max) t rpre t rp s t c l = 2 t a c ( max) d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t a c ( min) t lz ( max)
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 75 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 48: bank write ? without auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c ommand 5 3 a c t ra ra c ol n write 2 nop 6 one bank all bank s bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm n d in t d s t dh don ? t c are tran s itionin g data t dq ss (nom) t wpre t wpre s a0?a9 a11, a12
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 76 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 49: bank write ? with auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. enable auto precharge. 4. pre = precharge; act = active; ra = row address; ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 5 nop 5 command 4 3 act ra ra col n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dqsl t dqsh t wpst dq 1 dqs dm d in n t ds t dh t dqss (nom) don?t care transitioning data t wpres t wpre a0?a9 a11, a12
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 77 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram timing diagrams advance figure 50: write ? dm operation notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge; act = active; ra = row address; ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c ommand 5 3 a c t ra ra c ol n write 2 nop 6 one bank all bank s bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm d in n t d s t dh don ? t c are tran s itionin g data t dq ss (nom) a0 ?a 9 a11, a12 t wpres t wpre
pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 78 ?2007 micron technology, inc. all rights reserved. 1gb: x16, x32 mobile ddr sdram package dimensions advance package dimensions figure 51: 60-ball vfbga package notes: 1. all dimensions are in millimeters. ball a1 id mold c ompound: epoxy novola c s ub s trate: pla s ti c laminate ball a1 ball a1 id c l c l 0.10 c c 0. 6 5 0.05 6 0x ? 0.45 ball a9 7.20 3. 6 0 5.75 0.05 11.50 0.10 0.80 typ 0.80 typ 6 .40 3.20 5.00 0.05 10.00 0.10 1.00 max s eatin g plane s older ball material: 9 6 .5 % s n, 3 % a g , 0.5 % c u s older ball pad: ?0.40 s older ma s k defined s older ball diameter refer s to po s t reflow c ondition. the pre-reflow diameter i s ?0.42.
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains initial descript ions of products still under development. 1gb: x16, x32 mobile ddr sdram package dimensions pdf: 09005aef82846a0b/source: 09005aef828c2f8f micron technology, inc., reserves the right to change products or specifications without notice. 1gb_ddr_mobile_sdram_t48m_2.fm - rev. a 02/07 en 79 ?2007 micron technology, inc. all rights reserved. advance figure 52: 90-ball vfbga package notes: 1. all dimensions are in millimeters. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu ball a9 0.80 typ 5.60 0.65 0.05 seating plane a 11.20 6.40 0.10 a 90x ?0.45 dimensions apply to solder balls post reflow. the pre-reflow diameter is 0.42 on a 0.40 smd ball pad. c l 13.00 0.10 ball a1 ball a1 id 0.80 typ 6.50 0.05 c l 3.20 10.00 0.10 5.00 0.05

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